Software / Hardware Engineer - Fremont, California, United States

IT Jobs Fremont, California, United States
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Description

TetraMem is a fast-growing well-funded startup company working on the next generation of computing platforms with unique ReRAM-based in-memory computing technologies. We are hiring in multiple positions from software to hardware.

In this role you will be part of a world-class IC design team responsible for the development and deployment of hardware solutions for a revolutionary computing system, which we believe can reduce the energy consumption of AI processing by two orders of magnitude over conventional digital solutions. This will completely disrupt the AI IoT landscape. It is based on our unique computing memory device with multi-bit-level capacity per cell, which is nonvolatile with excellent retention and endurance. We offer a very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, daycare subsidy, and other perks.

Multiple job openings including Engineer, Senior Engineer, Staff Engineer, Senior Staff Engineer,
Principal Engineer, Senior Principal Engineer, etc. position levels are determined by background and experience.

Analog/Mixed-Signal IC Designer

Requirements:
MS or PhD in Electrical Engineering with emphasis on CMOS analog/mixed-signal integrated circuit design
5+ years of experience in analog or mixed-signal IC development in advanced CMOS processes (PhD experience may be considered as experience), successful tape-out experience with leading foundries
Strong knowledge in analog/mixed signal circuits such as OpAmps, bandgap, voltage/current references
Familiar with common EDA environment tools, CAD tools and Analog design methodology including design, simulation, layout, and verification tools (e.g., Synopsys, Cadence, Mentor Graphics etc.)
In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
Hands-on experience with analog mixed-signal IC development from definition to high-volume production including layout supervision and bench characterization
Ability to create innovative architecture and circuit solutions to meet customer requirements
Ability to work in a startup environment and to work both independently and as a team player

Experience in one or more of the following areas considered a strong plus:
Hands-on experience in data converter (ADC/DAC) design and techniques
Hands-on experience in memory design or in-memory computing circuit design
Hands-on experience in AMS design and verification methodology

Device Testing Engineer

Responsibilities:
As a Device Test Engineer, the responsibilities include, but are not limited to the following:
Develop test software based on memristor devices.
Automate testing flows, reduce testing time and write scripts in data parsing.
Define test flow and characterize chip functionalities with high quality standards.
Generate test and characterization reports with statistics analysis for process DOE (Design of Experiments)
Participate in troubleshooting and support design/device/process engineers in all testing activities.
Must be able to manage project progress and meet deadlines.
Perform debug and failure analyses during manufacturing builds and participate in continuous improvements in product manufacturability and testability, contributing to the production of the highest quality products
Perform maintenance of lab equipment periodically

EDUCATION REQUIREMENTS/ PREFERENCE
This position requires a Master’s degree (in CS or related field) with a minimum 3+ years of related experience.
Experiences of Non-volatile memory (such as RRAM, PRAM, FLASH, and MRAM)
Experiences advanced node CMOS characterization
Hardware bring-up, characterization, validation, and deployment to external vendor
Individuals should have extensive experience in testing, and characterization labs.
At least three years of demonstrable experience with hardware testing, and using lab/test equipment (e.g. oscilloscope, waveform generators, …) and performing test data analysis
Extensive knowledge in design of experiments, statistical methods, and data analysis is a must.
Strong knowledge of semiconductor product testing and characterization equipment
The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment.
Self-motivated, self-directed, however, must have demonstrated the ability to work well with people.
The candidate must have a proven desire to work as a team member, both on the same team and outside of the team, and within a cross-functional environment.
Should be able to troubleshoot, multi-task and meet deadlines.
Excellent communication (written and verbal) and interpersonal skills.
Experience in wafer, die and package handling
Experience with semi-automated and automated processing tools (ATE and Wafer probe)
Proficient in C/C++. Knowledge of Python is a plus.

Analog Layout Lead Engineer

Key Responsibilities:
Lead a team of layout engineers to produce complex analog and mixed-signal blocks with high-quality layout
Collaborate with project managers and design engineers to understand project requirements
Drive critical floor-planning decisions and key layout methodology
Ensure that all designs meet project requirements and adhere to design guidelines
Review and approve final layout designs for production
Stay up-to-date with industry trends and advancements in design software and techniques
Attend project meetings, presentations, and other events as needed

Requirements:
B.S. EE and 8+ years of relevant industry experience or equivalent
Experience in analog and mixed-signal layout design of deep submicron CMOS circuits and recent experience on advance nodes
Proficiency in industry-standard design software, such as Cadence Virtuoso, Calibre DRC, LVS
Strong understanding of layout design principles and best practices
Excellent communication, collaboration, and leadership skills
Ability to manage multiple projects simultaneously while maintaining attention to detail
Demonstrated ability to work independently and as part of a team
Strong problem-solving and decision-making skills

Sr.Design Verification Engineer

Responsibilities:
Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification.
Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance.
Develop reusable testbench, constrained-random/directed test cases, and verification associated behavioral modules for both block levels and system levels.
Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out.
Work with design engineers to debug and identify root causes of simulation failure.
Support test engineers for post-silicon validation.
Mentor and coach team members and junior engineers. Drive verification efficiency.

Qualifications:
MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree.
In depth knowledge of UVM/OVM, Semi Formal Verification, assertion-based verification as well as hardware and software co-verification methodology.
Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and test cases development for function/performance verification.
Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding.
Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core.
Experience in verifying designs at both RTL level and post-P&R gate level.
Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team.

ML Model Software Engineer

Responsibilities:
Develop innovative techniques for model compression
Optimize neural network architectures to leverage our revolutionary new hardware design
Implement, train, and improve ML models
Senior candidates will lead and mentor in a growing team

Requirements:
MS or PhD with published research work in ML model optimization, post-training quantization, consideration of different datasets and different constraints (bit-accuracy, model size, latency and so on).
Experience with popular machine learning frameworks, such as PyTorch and TensorFlow
Startup mindset/experience

Experience in one or more of the following areas considered a strong plus:
Experience with popular light-weight ML models on edge inference
Hands-on experiences with deploying/evaluating ML models on resource/power-limited computing platforms.
Experience providing technical leadership and/or guidance to other engineers

Please send your resume to hrteam@tetramem.com with your resume and point out your interested position, thanks!
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  • do NOT contact us with unsolicited services or offers

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Listing id 24155
Post date 05/09/2023 15:16

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